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ISL85001
Data Sheet November 17, 2008 FN6769.0
1A Standard Buck PWM Regulator
The ISL85001 is a high-performance, simple output controller that provides a single, high frequency power solution for a variety of point-of-load applications. The ISL85001 integrates a 1A standard buck PWM controller and switching MOSFET. The PWM controller in the ISL85001 drives an internal switching N-Channel power MOSFET and requires an external Schottky diode to generate an output voltage from 0.6V to 19V. The integrated power switch is optimized for excellent thermal performance for up to 1A of output current. The standard buck input voltage range supports a fixed 5V or variable 5.5V to 25V range. The PWM regulator switches at a fixed frequency of 500kHz and utilizes simple voltage mode control with input voltage feed-forward to provide flexibility in component selection and minimize solution size. Protection features include overcurrent, undervoltage and thermal overload protection integrated into the IC. The ISL85001 power-good signal output indicates loss of regulation on the PWM output. ISL85001 is available in a small 4mmx3mm Dual Flat No-Lead (DFN) package.
Features
* Standard Buck Controller with Integrated Switching Power MOSFET * Integrated Boot Diode * Input Voltage Range - Fixed 5V 10% - Variable 5.5V to 25V * PWM Output Voltage Adjustable from 0.6V to 19V with Continuous Output Current up to 1A * 1% VFB Tolerance * Voltage Mode Control with Voltage Feed-Forward * Fixed 500kHz Switching Frequency * Externally Adjustable Soft-Start Time * Output Undervoltage Protection * Enable Inputs * PGOOD Output * Overcurrent Protection * Thermal Overload Protection * Internal 5V LDO Regulator * Pb-Free (RoHS compliant)
Ordering Information
PART NUMBER (Note) ISL85001IRZ PART MARKING 501Z TEMP. RANGE (C) -40 to +85 -40 to +85 PACKAGE (Pb-free) 12 Ld DFN 12 Ld DFN PKG. DWG. # L12.4x3 L12.4x3
Applications
* General Purpose * WLAN Cards-PCMCIA, Cardbus32, MiniPCI Cards-Compact Flash Cards * Hand-Held Instruments * LCD Panel * Set-top Box
ISL85001IRZ-T* 501Z
*Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinout
ISL85001 (12 LD 4X3 DFN) TOP VIEW
FB COMP SS EN PG GND
1 2 3 4 5 6 GND
12 VIN 11 VIN
10 PHASE 9 8 7 PHASE BOOT VDD
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL85001 Typical Application Schematic
R3 301 R1 10k C1 10pF C3 100pF VOUT R4 3.16k C2 2.2nF R2 31k COMP FB
C5 0.1F SS
VIN C9 10F EN L 22H
5.5V TO 25V
PG
ISL85001
PHASE C10 0.1F
VOUT = 2.5V C11 47F D B340LB
BOOT GND VDD C13 1 F
FIGURE 1. VIN RANGE FROM 5.5V TO 25V
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ISL85001 Functional Block Diagram
COMP BOOT VDD VDD SOFT-START CONTROL OC MONITOR VIN (x2) PWM EA + VIN GATE DRIVE FB 30A + THERMAL MONITOR +150C OC MONITOR POR VIN VDD PG LDO POWER-ON RESET MONITOR VDD VOLTAGE MONITOR SS 0.6V REFERENCE FAULT MONITOR RAMP GENERATOR
PHASE (x2)
EN
OSCILLATOR
GND
EPAD GND
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ISL85001
Absolute Maximum Ratings (Note 1)
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 26V BOOT to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 33V BOOT to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.03V to 6V VDD, FB, EN, COMP, PG, SS . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
Thermal Information
Thermal Resistance JA (C/W) JC (C/W) QFN Package (Notes 1, 2). . . . . . . . . . 39 3 Ambient Temperature Range. . . . . . . . . . . . . . . . . . .-40C to +85C Junction Temperature Range. . . . . . . . . . . . . . . . . .-40C to +125C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . 4.5V to 25V Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 1A Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . -40C to +85
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379 for details. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Typical Specifications are Measured at the Following Conditions: TA = -40C to +85C. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER SUPPLY VOLTAGE VIN Voltage Range
VIN VIN connected to VDD
5.5 4.5 -
5.0 2 80
25 5.5 2.5 100
V V mA A
VIN Operating Supply Current VIN Shutdown Supply Current POWER-ON RESET VDD POR Threshold
IOP ISD
(Note 2) VIN = 15V, EN = GND
Rising Edge Hysteresis
4.00 -
4.15 275
4.30 -
V mV
INTERNAL VDD LDO VDD Output Voltage Range REFERENCE Reference Voltage STANDARD BUCK PWM REGULATOR FB Line Regulation FB Leakage Current OSCILLATOR AND PWM MODULATOR Nominal Switching Frequency Modulator Gain Peak-to-Peak Sawtooth Amplitude PWM Ramp Offset Voltage Maximum Duty Cycle ERROR AMPLIFIER Open-Loop Gain Gain Bandwidth Product Slew Rate ENABLE SECTION GBWP SR COMP = 10pF 88 15 5 dB MHz V/s fSW AMOD VRAMP VOFFSET DCmax COMP > 4V VIN = 12V (AMOD = 8/VIN) VIN = 12V (VP-P = VIN/8) 450 0.65 0.75 80 500 0.75 1.3 0.8 550 0.95 0.85 kHz V/V V V % IOUT = 0mA, VIN = 5.5V to 25V VFB = 0.6V -0.05 -50 0 0.05 50 % nA VFB VIN = 5.5V to 25V, IREF = 0 0.594 0.6 0.606 V VIN = 5.5V to 25V, IVDD = 0mA to 30mA 4.5 5.00 5.5 V
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Electrical Specifications
Typical Specifications are Measured at the Following Conditions: TA = -40C to +85C. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) SYMBOL Rising Edge Hysteresis EN Logic Input Current FAULT PROTECTION Thermal Shutdown Temperature TSD THYS PWM UV Trip Level PWM UVP Propagation Delay PWM OCP Threshold OCP Blanking Time POWER-GOOD PG Trip Level Referred to Nominal VOUT Lower Level, Falling Edge, with typically 15mV hysteresis Upper Level, Rising Edge, with typically 15mV hysteresis PG Propagation Delay PG Low Voltage PG Leakage Current SOFT-START SECTION Soft-Start Threshold to Enable Buck Soft-Start Threshold to Enable PG Soft-Start Voltage High Soft-Start Charging Current Soft-Start Pull-down POWER MOSFET rDS(ON) NOTES: 3. Test Condition: VIN = 15V, FB forced above regulation point (0.6V), no switching, and power MOSFET gate charging current not included. 4. Excluding the blanking time. IOUT = 100mA, Die Resistance 120 200 m VSS = 3.0V 0.9 2.5 20 1 3.0 3.45 30 25 1.1 3.5 40 V V V A mA ISINK = 4mA VPG = 5.5V, VFB = 0.6V, VDD = 5.5V 85 108 -1 88 112 9 0.05 91 116 0.3 1 % % s V A VIN = VDD = 5V, (Note 4) VUV Rising Threshold Hysteresis Referred to Nominal VOUT 70 1.37 150 15 75 270 1.7 100 80 2.17 C C % ns A ns TEST CONDITIONS MIN 1.2 -1 TYP 1.7 400 MAX 2.2 1 UNITS V mV A
PARAMETER EN Threshold
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ISL85001 Pin Descriptions
FB (Pin 1) and COMP (Pin 2)
The standard buck regulator employs a single voltage control loop. FB is the negative input to the voltage loop error amplifier. COMP is the output of the error amplifier. The output voltage is set by an external resistor divider connected to FB. With a properly selected divider, the output voltage can be set to any voltage between the power rail (reduced by converter losses) and the 0.6V reference. Connecting an AC network across COMP and FB provides loop compensation to the amplifier. In addition, the PWM regulator power-good and undervoltage protection circuitry use FB to monitor the regulator output voltage.
GND (Pin 6)
Ground connect for the IC and thermal relief for the package. The exposed pad must be connected to GND and soldered to the PCB. All voltage levels are measured with respect to this pin.
VDD (Pin 7)
Internal 5V linear regulator output provides bias to all the internal control logic. The ISL85001 may be powered directly from a 5V (10%) supply at this pin. When used as a 5V supply input, this pin must be externally connected to VIN. The VDD pin must always be decoupled to GND with a ceramic bypass capacitor (minimum 1F) located close to the pin.
TABLE 1. INPUT SUPPLY CONFIGURATION INPUT 5.5V to 25V PIN CONFIGURATION Connect the input supply to the VIN pin only. The VDD pin will provide a 5V output from the internal linear regulator. Connect the input supply to the VIN and VDD pins.
SS (Pin 3)
Program pin for soft-start duration. A regulated 30A pull-up current source charges a capacitor connected from the pin to GND. The output voltage of the converter follows the ramping voltage on the SS pin.
5V 10%
EN (Pin 4)
PWM controller enable input. The PWM converter output is held off when the pin is pulled to ground. When the voltage on this pin rises above 1.7V, the chip is enabled.
BOOT (Pin 8)
Floating bootstrap supply pin for the power MOSFET gate driver. The bootstrap capacitor provides the necessary charge to turn and hold on the internal N-Channel MOSFET. Connect an external capacitor from this pin to PHASE.
PG (Pin 5)
PWM converter power-good output. Open drain logic output that is pulled to ground when the output voltage is outside regulation limits. Connect a 100k resistor from this pin to VDD. Pin is low when the buck regulator output voltage is not within 10% of the respective nominal voltage, or during the soft-start interval. Pin is high impedance when the output is within regulation.
PHASE (Pins 9, 10)
Switch node connections to internal power MOSFET source, external output inductor and external diode cathode.
VIN (Pins 11, 12)
The input supply for the PWM regulator power stage and the source for the internal linear regulator that provides bias for the IC. Place a ceramic capacitor from VIN to GND, close to the IC for decoupling (typical 10F).
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ISL85001 Typical Performance Curves
1.0 0.9 0.8 EFFICIENCY (%) 1.8VOUT 2.5VOUT 1.5VOUT EFFICIENCY (%) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.0 0.2 0.4 0.6 OUTPUT LOAD (A) 0.8 1.0 3.3VOUT
Unless otherwise noted, operating conditions are: TA = +25C, VIN = 12V, EN = VDD, L = 22H, C9 = 10F, C11 = 47F, IOUT = 0A to 1A. See "VIN (Pins 11, 12)" on page 6.
1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.0 0.2 0.4 0.6 OUTPUT LOAD (A) 0.8 1.0 1.2VOUT 1.5VOUT 1.8VOUT 2.5VOUT 5VOUT 3.3VOUT
FIGURE 2. EFFICIENCY vs LOAD, 500kHz, 5VIN
FIGURE 3. EFFICIENCY vs LOAD, 500kHz, 12VIN
1.0 0.9 0.8 EFFICIENCY (%) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.0 0.2 0.4 0.6 OUTPUT LOAD (A) 0.8 1.0 1.2VOUT 1.5VOUT 1.8VOUT 2.5VOUT 5VOUT POWER DISSIPATION (W)
0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 OUTPUT LOAD (A) 5VIN 0.7 0.8 0.9 1.0 25VIN 12VIN
FIGURE 4. EFFICIENCY vs LOAD, 500kHz, 25VIN
FIGURE 5. POWER DISSIPATION vs LOAD, 500kHz, 2.5VOUT
1.206 1.205 OUTPUT VOLTAGE (V) 1.204 1.203 1.202 1.201 1.200 1.199 1.198 0.0 0.2 0.4 0.6 OUTPUT LOAD (A) 0.8 1.0 5VIN 25VIN 12VIN OUTPUT VOLTAGE (V)
1.510 1.509 25VIN 1.508 1.507 1.506 1.505 1.504 1.503 1.502 0.0 0.2 0.4 0.6 OUTPUT LOAD (A) 0.8 1.0 5VIN 12VIN
FIGURE 6. VOUT REGULATION vs LOAD, 500kHz, 1.2VOUT
FIGURE 7. VOUT REGULATION vs LOAD, 500kHz, 1.5VOUT
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ISL85001 Typical Performance Curves
1.814 1.813 OUTPUT VOLTAGE (V) 1.812 1.811 1.810 1.809 1.808 1.807 1.806 0.0 0.2 0.4 0.6 OUTPUT LOAD (A) 0.8 1.0 5VIN 25VIN 12VIN
Unless otherwise noted, operating conditions are: TA = +25C, VIN = 12V, EN = VDD, L = 22H, C9 = 10F, C11 = 47F, IOUT = 0A to 1A. See "VIN (Pins 11, 12)" on page 6. (Continued)
2.506 2.505 OUTPUT VOLTAGE (V) 2.504 2.503 2.502 2.501 2.500 2.499 2.498 0.0 0.2 5VIN 0.4 0.6 OUTPUT LOAD (A) 0.8 1.0 25VIN 12VIN
FIGURE 8. VOUT REGULATION vs LOAD, 500kHz, 1.8VOUT
FIGURE 9. VOUT REGULATION vs LOAD, 500kHz, 2.5VOUT
3.330 3.328 OUTPUT VOLTAGE (V) 3.326 3.324 3.322 3.320 3.318 3.316 3.314 0.0 0.2 0.4 0.6 OUTPUT LOAD (A) 0.8 1.0 7VIN 25VIN 12VIN OUTPUT VOLTAGE (V)
4.99 4.98 4.97 4.96 4.95 4.94 4.93 4.92 4.91 0.1 0.3 12VIN 0.5 0.7 OUTPUT LOAD (A) 0.9 7VIN 25VIN
FIGURE 10. VOUT REGULATION vs LOAD, 500kHz, 3.3VOUT
FIGURE 11. VOUT REGULATION vs LOAD, 500kHz, 5VOUT
PHASE 5V/DIV PHASE 5V/DIV
VOUT RIPPLE 20mV/DIV
VOUT RIPPLE 20mV/DIV
IL 0.1A/DIV
IL 0.5A/DIV
FIGURE 12. STEADY STATE OPERATION AT NO LOAD (5s/DIV)
FIGURE 13. STEADY STATE OPERATION AT FULL LOAD (1s/DIV)
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ISL85001 Typical Performance Curves
PHASE 10V/DIV
Unless otherwise noted, operating conditions are: TA = +25C, VIN = 12V, EN = VDD, L = 22H, C9 = 10F, C11 = 47F, IOUT = 0A to 1A. See "VIN (Pins 11, 12)" on page 6. (Continued)
EN 5V/DIV
VOUT 2V/DIV VOUT RIPPLE 100mV/DIV IL 0.5A/DIV PG 5V/DIV IL 0.5A/DIV SS 5V/DIV
FIGURE 14. LOAD TRANSIENT (200s/DIV)
FIGURE 15. SOFT-START AT NO LOAD (2ms/DIV)
EN 5V/DIV
EN 5V/DIV
VOUT 2V/DIV
IL 0.5A/DIV
VOUT 2V/DIV IL 1A/DIV PG 5V/DIV SS 5V/DIV PG 5V/DIV
FIGURE 16. SOFT-START AT FULL LOAD (2ms/DIV)
FIGURE 17. SHUT DOWN CIRCUIT (100s/DIV)
PHASE 10V/DIV PHASE 10V/DIV
VOUT 1V/DIV VOUT 1V/DIV
IL 1A/DIV
IL 1A/DIV PG 5V/DIV PG 5V/DIV
FIGURE 18. OUTPUT SHORT CIRCUIT (5s/DIV)
FIGURE 19. OUTPUT SHORT CIRCUIT RECOVERY (1ms/DIV)
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ISL85001 Detailed Description
The ISL85001 combines a standard buck PWM controller with an integrated switching MOSFET. The buck controller drives an internal N-Channel MOSFET and requires an external diode to deliver load current up to 1A. A Schottky diode is recommended for improved efficiency and performance over a standard diode. The standard buck regulator can operate from either an unregulated DC source, such as a battery, with a voltage ranging from +5.5V to +25V, or from a regulated system rail of +5V. When operating from +5.5V or greater, the controller is biased from an internal +5V LDO voltage regulator. The converter output is regulated down to 0.6V from either input source. These features make the ISL85001 ideally suited for FPGA and wireless chipset power applications. The PWM control loop uses a single output voltage loop with input voltage feed forward, which simplifies feedback loop compensation and rejects input voltage variation. External feedback loop compensation allows flexibility in output filter component selection. The regulator switches at a fixed 500kHz. The buck regulator is equipped with a lossless current limit scheme. The current limit in the buck regulator is achieved by monitoring the drain-to-source voltage drop of the internal switching power MOSFET. The current limit threshold is internally set at 1.7A. The part also features undervoltage protection by latching the switching MOSFET driver to the OFF-state during an overcurrent, when the output voltage is lower than 70% of the regulated output. This helps minimize power dissipation during a short-circuit condition. Due to only the switching power MOSFET integration, there is no overvoltage protection feature for this part.
Power-On Reset and Undervoltage Lockout
The PWM portion of the ISL85001 automatically initializes upon receipt of input power. The power-on reset (POR) function continually monitors the VDD voltage. While below the POR thresholds, the controller inhibits switching off the internal power MOSFET. Once exceeded, the controller initializes the internal soft-start circuitry. If either input supply drops below their falling POR threshold during soft-start or operation, the buck regulator latches off.
Enable and Disable
All internal power devices are held in a high-impedance state, which ensures they remain off while in shutdown mode. Typically, the enable input for a specific output is toggled high after the input supply to that regulator is active and the internal LDO has exceeded it's POR threshold. The EN pin enables the buck controller portion of the ISL85001. When the voltage on the EN pin exceeds the POR rising threshold, the controller initiates the soft-start function for the PWM regulator. If the voltage on the EN pin drops below the POR falling threshold, the buck regulator shuts down. Pulling the EN pin low simultaneously put the output into shutdown mode and supply current drops to 100A typical.
Soft-Start
Once the input supply latch and enable threshold are met, the soft-start function is initialized. The soft-start circuitry begins sourcing 30A, from an internal current source, which charges the external soft-start capacitor. The voltage on SS begins ramping linearly from ground until the voltage across the soft-start capacitor reaches 3.0V. This linear ramp is applied to the non-inverting input of the internal error amplifier and overrides the nominal 0.6V reference. The output voltage reaches its regulation value when the soft-start capacitor voltage reaches 1.6V. Connect a capacitor from SS pin to ground. This capacitor (along with an internal 30A current source) sets the soft-start interval of the converter, tSS.
C SS [ F ] = 50 t SS [ s ] (EQ. 1)
+5V Internal Bias Supply (VDD)
Voltage applied to the VIN pin with respect to GND is regulated to +5V DC by an internal LDO regulator. The output of the LDO, VDD, is the bias voltage used by all the internal control and protection circuitry. The VDD pin requires a ceramic capacitor connected to GND. The capacitor serves to stabilize the LDO and to decouple load transients. The input voltage range for the ISL85001 is specified as +5.5V to +25V or +5V 10%. In the case of an unregulated supply case, the power supply is connected to VIN only. Once enabled, the linear regulator will turn-on and rise to +5V on VDD. In the +5V supply case, the VDD and VIN pins must be tied together to bypass the LDO. The external decoupling capacitor is still required in this mode.
Upon disable, the SS pin voltage will discharge to zero voltage.
Power-Good
PG is an open-drain output of a window comparator that continuously monitors the buck regulator output voltage. PG is actively held low when EN is low and during the buck regulator soft-start period. After the soft-start period terminates, PG becomes high impedance as long as the output voltage is within 12% of the nominal regulation voltage set by FB. When VOUT drops 12% below or rises 12% above the nominal regulation voltage, the ISL85001 pulls PG low. Any fault condition forces PG low until the fault condition is cleared by attempts to soft-start. For logic level output voltages, connect an external pull-up resistor between PG and VDD. A 100k resistor works well in most applications.
Operation Initialization
The power-on reset circuitry and enable inputs prevent false start-up of the PWM regulator output. Once all the input criteria are met, the controller soft-starts the output voltage to the programmed level.
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Output Voltage Selection
The regulator output voltages can be programmed using external resistor dividers that scale the voltage feedback relative to the internal reference voltage. The scaled voltage is fed back to the inverting input of the error amplifier; refer to Figure 20. The output voltage programming resistor, R4, will depend on the value chosen for the feedback resistor, R1, and the desired output voltage, VOUT, of the regulator; see Equation 2. The value for the feedback resistor is typically between 1k and 10k.
R 1 x 0.6V R 4 = ---------------------------------V OUT - 0.6V (EQ. 2)
cycles, the overcurrent fault counter overflows, indicating an overcurrent fault condition exists. The regulator is shut down and power-good goes low. If the overcurrent condition clears prior to the counter reaching four consecutive cycles, the internal flag and counter are reset. The protection circuitry attempts to recover from the overcurrent condition after waiting 4 soft-start cycles. The internal overcurrent flag and counter are reset. A normal soft-start cycle is attempted and normal operation continues if the fault condition has cleared. If the overcurrent fault counter overflows during soft-start, the converter shuts down and this hiccup mode operation repeats. There is 100ns blanking time for noise immunity. It is recommended to operate the duty cycle higher than the blanking time to insure proper overcurrent protection.
If the output voltage desired is 0.6V, then RP is left unpopulated.
VOUT R1 + -
Undervoltage Protection
If the voltage detected on the buck regulator FB pin falls 25% below the internal reference voltage, the undervoltage fault condition flag is set. The regulator is shutdown. The controller enters a recovery mode similar to the overcurrent hiccup mode. No action is taken for 4 soft-start cycles and the internal undervoltage counter and fault condition flag are reset. A normal soft-start cycle is attempted and normal operation continues if the fault condition has cleared. If the undervoltage counter overflows during soft-start, the converter is shut down and this hiccup mode operation repeats.
EA
R4
0.6V REFERENCE
FIGURE 20. EXTERNAL RESISTOR DIVIDER
The buck output can be programmed as high as 19V. Proper heatsinking must be provided to insure that the junction temperature does not exceed +125C. When the output is set greater than 2.7V, it is recommended to pre-load at least 10mA and make sure that the input rise time is much faster than the VOUT1 rise time. This allows the BOOT capacitor adequate time to charge for proper operation.
Thermal Overload Protection
Thermal overload protection limits total power dissipation in the ISL85001. There is a sensor on the chip to monitor the junction temperature of the internal LDO and PWM switching power N-Channel MOSFET. When the junction temperature (TJ) of the sensor exceeds +150C, the thermal sensor sends a signal to the fault monitor. The fault monitor commands the buck regulator to shut down. The buck regulator soft-starts turn on again after the IC's junction temperature cools by +20C. The buck regulator experiences hiccup mode operation during continuous thermal overload conditions. For continuous operation, do not exceed the +125C junction temperature rating.
Protection Features
The ISL85001 limits current in the power devices to limit on-chip power dissipation. Overcurrent limits on the regulator protect the internal power device from excessive thermal damage. Undervoltage protection circuitry on the buck regulator provides a second layer of protection for the internal power device under high current condition.
Buck Regulator Overcurrent Protection
During the PWM on-time, the current through the internal switching MOSFET is sampled and scaled through an internal pilot device. The sampled current is compared to a nominal 1.7A overcurrent limit. If the sampled current exceeds the overcurrent limit reference level, an internal overcurrent fault counter is set to 1 and an internal flag is set. The internal power MOSFET is immediately turned off and will not be turned on again until the next switching cycle. The protection circuitry continues to monitor the current and turns off the internal MOSFET as described. If the overcurrent condition persists for eight sequential clock
Application Guidelines
Operating Frequency
The ISL85001 operates at a fixed switching frequency of 500kHz.
Buck Regulator Output Capacitor Selection
An output capacitor is required to filter the inductor current and supply the load transient current. The filtering requirements are a function of the switching frequency and the ripple current. The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the
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transient load current. These requirements are generally met with a mix of capacitors and careful layout. Embedded processor systems are capable of producing transient load rates above 1A/ns. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (Effective Series Resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. Use only specialized low-ESR capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor's ESR will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. An aluminum electrolytic capacitor's ESR value is related to the case size with lower ESR available in larger case sizes. However, the Equivalent Series Inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor's impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. The response time to a transient is different for the application of load and the removal of load. Equation 4 gives the approximate response time interval for application and removal of a transient load:
tRISE = L x ITRAN VIN - VOUT tFALL = L x ITRAN VOUT (EQ. 4)
where: ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. The worst case response time can be either at the application or removal of load. Be sure to check Equation 4 at the minimum and maximum output levels for the worst case response time.
Rectifier Selection
Current circulates from ground to the junction of the MOSFET and the inductor when the high-side switch is off. As a consequence, the polarity of the switching node is negative with respect to ground. This voltage is approximately -0.5V (a Schottky diode drop) during the off-time. The rectifier's rated reverse breakdown voltage must be at least equal to the maximum input voltage, preferably with a 20% derating factor. The power dissipation is shown in Equation 5:
V OUT P D [ W ] = I OUT V D 1 - --------------- V IN (EQ. 5)
where VD is the voltage of the Schottky diode = 0.5V to 0.7V
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time the switching MOSFET turns on. Place the small ceramic capacitors physically close to the MOSFET VIN pins (switching MOSFET drain) and the Schottky diode anode. The important parameters for the bulk input capacitance are the voltage rating and the RMS current rating. For reliable operation, select bulk capacitors with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. Their voltage rating should be at least 1.25 times greater than the maximum input voltage, while a voltage rating of 1.5 times is a conservative guideline. For most cases, the RMS current rating requirement for the input capacitor of a buck regulator is approximately 1/2 the DC load current. The maximum RMS current required by the regulator may be closely approximated through Equation 6:
I RMS
MAX
Output Inductor Selection
The output inductor is selected to meet the output voltage ripple requirements and minimize the converter's response time to the load transient. The inductor value determines the converter's ripple current and the ripple voltage is a function of the ripple current. The ripple voltage and current are approximated by Equation 3:
I = VIN - VOUT Fs x L x VOUT VIN VOUT = I x ESR (EQ. 3)
Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance values reduce the converter's response time to a load transient. One of the parameters limiting the converter's response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the ISL85001 will provide either 0% or 80% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level. During this interval, the difference between the inductor current and the transient current level must be supplied by the output capacitor. Minimizing the response time can minimize the output capacitance required.
=
V OUT V IN - V OUT V OUT 2 2 1 ------------- x I OUT + ----- x ---------------------------- x ------------- L x fs V IN V IN 12 MAX (EQ. 6)
For a through-hole design, several electrolytic capacitors may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These
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12
ISL85001
capacitors must be capable of handling the surge-current at power-up. Some capacitor series available from reputable manufacturers are surge current tested.
OSC DRIVER VIN LO PHASE D CO VDDQ PWM COMPARATOR +
C3) in Figure 22. Use the following guidelines for locating the poles and zeros of the compensation network: 1. Pick Gain (R2/R1) for desired converter bandwidth. 2. Place 1ST Zero Below Filter's Double Pole (~75% FLC). 3. Place 2ND Zero at Filter's Double Pole. 4. Place 1ST Pole at the ESR Zero. 5. Place 2ND Pole at Half the Switching Frequency. 6. Check Gain against Error Amplifier's Open-Loop Gain. 7. Estimate Phase Margin - Repeat if Necessary.
VOSC
ZFB VE/A + ERROR AMP ZIN REFERENCE
ESR (PARASITIC)
Compensation Break Frequency Equations
1 F Z1 = ----------------------------------2 x R 2 x C 2 1 F P1 = ------------------------------------------------------- C 1 x C 2 2 x R 2 x --------------------- C1 + C2 1 F P2 = ----------------------------------2 x R 3 x C 3
DETAILED COMPENSATION COMPONENTS C1 C2 COMP + ISL85001 REFERENCE FB R4 R2 ZFB ZIN C3 R1 R3 VOUT
1 F Z2 = -----------------------------------------------------2 x ( R 1 + R 3 ) x C 3
(EQ. 8)
FIGURE 21. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN AND OUTPUT VOLTAGE SELECTION
Feedback Compensation
Figure 21 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage (VOUT) is regulated to the Reference voltage level. The error amplifier output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulse-width modulated (PWM) wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (LO and CO). The modulator transfer function is the small-signal transfer function of VOUT/VE/A . This function is dominated by a DC Gain and the output filter (LO and CO), with a double pole break frequency at FLC and a zero at FESR . The DC Gain of the modulator is simply the input voltage (VIN) divided by the peak-to-peak oscillator voltage VOSC .
Figure 22 shows an asymptotic plot of the DC/DC converter's gain vs frequency. The actual Modulator Gain has a high gain peak due to the high Q factor of the output filter and is not shown in Figure 22. Using the previously mentioned guidelines should give a Compensation Gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabilities of the error amplifier. The Closed Loop Gain is constructed on the graph of Figure 4 by adding the Modulator Gain (in dB) to the Compensation Gain (in dB). This is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain.
100 80 60 GAIN (dB) 40 20 0 -20 -40 FLC -60 10 100 1k 10k FESR 100k 1M 10M MODULATOR GAIN 20LOG (R2/R1) OPEN LOOP ERROR AMP GAIN FZ1 FZ2 FP1 FP2
20LOG (VIN/VOSC) COMPENSATION GAIN CLOSED LOOP GAIN
Modulator Break Frequency Equations
1 F LC = -----------------------------------------2 x L O x C O 1 F ESR = ------------------------------------------2 x ESR x C O (EQ. 7)
FREQUENCY (Hz)
The compensation network consists of the error amplifier (internal to the ISL85001) and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency (f0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at f0dB and 180. Equation 8 relates the compensation network's poles, zeros and gain to the components (R1 , R2 , R3 , C1 , C2 , and 13
FIGURE 22. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
The compensation gain uses external impedance networks ZFB and ZIN to provide a stable, high bandwidth (BW) overall loop. A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45. Include worst case component variations when determining phase margin.
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ISL85001
A more detailed explanation of voltage mode control of a buck regulator can be found in TB417, entitled "Designing Stable Compensation Networks for Single Phase Voltage Mode Buck Regulators." http://www.intersil.com/data/tb/tb417.pdf
ISL85001 L 5V CBP1 VDD PHASE D GND COMP C2 R2 FB R4 GND PAD C3 R3 C1 R1 COUT1 LOAD
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VIN VIN CIN
Layout Considerations
Layout is very important in high frequency switching converter design. With power devices switching efficiently between 100kHz and 600kHz, the resulting current transitions from one device to another cause voltage spikes across the interconnecting impedances and parasitic circuit elements. These voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device overvoltage stress. Careful component layout and printed circuit board design minimizes these voltage spikes. As an example, consider the turn-off transition of the upper MOSFET. Prior to turn-off, the MOSFET is carrying the full load current. During turn-off, current stops flowing in the MOSFET and is picked up by the Schottky diode. Any parasitic inductance in the switched current path generates a large voltage spike during the switching interval. Careful component selection, tight layout of the critical components, and short, wide traces minimizes the magnitude of voltage spikes. There are two sets of critical components in the ISL85001 switching converter. The switching components are the most critical because they switch large amounts of energy, and therefore tend to generate large amounts of noise. Next are the small signal components, which connect to sensitive nodes or supply critical bypass current and signal coupling. A multi-layer printed circuit board is recommended. Figure 23 shows the connections of the critical components in the converter. Note that capacitors CIN and COUT could each represent numerous physical capacitors. Dedicate one solid layer, usually a middle layer of the PC board, for a ground plane and make all critical component ground connections with vias to this layer. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. Keep the metal runs from the PHASE terminals to the output inductor short. The power plane should support the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers for the phase nodes. Use the remaining printed circuit layers for small signal wiring. In order to dissipate heat generated by the internal LDO and MOSFET, the ground pad, pin 13, should be connected to the internal ground plane through at least four vias. This allows the heat to move away from the IC and also ties the pad to the ground plane through a low impedance path. The switching components should be placed close to the ISL85001 first. Minimize the length of the connections between the input capacitors, CIN, and the power switches by placing them nearby. Position both the ceramic and bulk 14
VOUT1
KEY ISLAND ON POWER PLANE LAYER ISLAND ON CIRCUIT AND/OR POWER PLANE LAYER VIA CONNECTION TO GROUND PLANE
FIGURE 23. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
input capacitors as close to the upper MOSFET drain as possible. Position the output inductor and output capacitors between the upper and Schottky diode and the load. The critical small signal components include any bypass capacitors, feedback components, and compensation components. Place the PWM converter compensation components close to the FB and COMP pins. The feedback resistors should be located as close as possible to the FB pin with vias tied straight to the ground plane as required.
ISL85001 Dual Flat No-Lead Plastic Package (DFN)
L12.4x3
2X A 0.15 C A D 2X 0.15 C B
12 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-229-VGED-4 ISSUE C) MILLIMETERS SYMBOL A A1 MIN 0.80 NOMINAL 0.90 0.20 REF 0.18 0.23 4.00 BSC 3.15 3.30 3.00 BSC 1.55 1.70 0.50 BSC 0.20 0.30 0.40 12 6 0.50 1.80 3.40 0.30 MAX 1.00 0.05 NOTES 5,8 7,8 7,8 8 2 3 Rev. 1 2/05
E 6 INDEX AREA TOP VIEW B
A3 b D D2 E E2
// 0.10 0.08 C C
e k
A SIDE VIEW C SEATING PLANE D2 (DATUM B) 6 INDEX AREA (DATUM A) E2/2 NX L N 8 N-1 e (Nd-1)Xe REF. BOTTOM VIEW (A1) 5 0.10 NX b 1 2 NX k E2 D2/2 A3
L N Nd NOTES:
7
8
1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd refers to the number of terminals on D. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389.
M C AB C L
NX (b) 5
L e
SECTION "C-C" TERMINAL TIP FOR EVEN TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 15
FN6769.0 November 17, 2008

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